laptopserviz
24-12-2011, 01:08 AM
Name
Type
Description
PWRBTN #
I
Power Button:. The power button will cause SMI # or SCI to indicate a system sleep state. If the system is asleep, then this signal will trigger a wake event. If PWRBTN # have effect when the room more than 4s, regardless of the system in the S0, S1, S3, S4 state, then will the unconditional transition to S5 state. This signal has an internal pull-up resistor and the input features of a 16ms debounce design.
RI #
I
Sound alert: This signal is a signal input from the Modem. It allows a wake-up event, when a power failure protection
SYS_RESET #
I
System Reset: This signal after the anti-rebound force an internal reset. If the SMBus is idle, South Bridge will be immediately reset, the other, forcing a reset in the system before, SYS_RESET # will wait for 25ms ± 2ms until the SMBus Free
RSMRST #
I
Restore normal reset signal:
This signal is used to reset the logic of power is restored, all the power of this signal is valid for at least 10ms will work, when the lift is valid, the signal is pending bus a sign of stability
LAN_RST #
I
LAN Reset:
When this signal is valid when the internal controller to reset the LAN, the LAN's ccLAN3_3 and VccLAN1_05 and VccCL3_3 normal state of the signal power to be effective. When the release is valid, the signal is a sign of a stable LAN Bus Notes: 1 lift effective in RSMRST # before LAN_RST # must be valid.
(2) effective after the PWROK, LAN_RST # must be valid.
3 in VccLAN3_3 and VccLAN1_05 and VccCL3_3 power under normal conditions are to be effective LAN_RST # 1ms.
4 Integrated LAN without LAN_RST # if it can be connected to Vss.
WAKE #
I
PCI Express * Wake Event: Sideband wake signal on the PCI Express slot and issue a wake-up request signal components
MCH_SYNC #
I
Northbridge sync signal: This input signal is phase with PWROK internally, and the signal is connected to the Northbridge ICH_SYNC # output.
SUS_STAT # / LPC PD #
O
Suspend state signal: This signal indicates that the system is about to enter an effective low-power state. It monitors these devices and the memory from the normal mode to enter the suspend mode, it can be used to isolate the output of other peripheral devices and turn them off, the signal in LPC I / F on the call LPCPD # to achieve.
SUSCLK
O
Hang the clock signal: This clock is RTC chip clock generator generates the clock through the other to the output.
VRMPWRGD
I
CPU Power Good Signal: This signal is directly connected to the CPU power management chip, the signal is normal that VRM is stable. The input signal is the phase of the internal PWROK.
This signal is normal at the time suspended
CK_PWRGD
O
Clock pulse generator power normal signal: When the main power efficient clock generator when the signal to go, when SLP_S3 # and VRMPWRGD two signals are high when the signal is active high
PMSYNC # (only for notebook) / GPIO0
O
Sync signal power management: When the signal is active, C5 or C6 in the exit when the signal from the North Bridge to CPUSLP # This pin is invalid.
This signal can also be used for GPIO.
CLKRUN # (only for notebook) / GPIO32 (only for desktop computers)
I / O
PCI clock run signal: This signal is used to support the PCI
CLKRUN agreement. When connected to external devices need to apply preventive restarting the clock or clock stopped
PLTRST #
O
Total reset signal: PLTRST # is Intel ® ICH9 always reset the entire platform (such as: I / O, BIOS chip, card, Northbridge, etc.). During power and when S / W reset control signal through the register (I / O registers CF9h) initiates a hard reset sequence ICH9 determine PLTRST # state. High in PWROK and VRMPWRGD ICH9 driver PLTRST # after at least 1 ms is invalid. When initialized by reset control register (I / O registers CF9h) when the ICH9 driver PLTRST # is valid for at least 1 millisecond.
Note: Only VccSus3_3 normal PLTRST # This signal is applied.
THRM #
I
Thermal alarm signal: activation THRM # signal to low external hardware to generate an SMI # or SCI signal
THRMTRIP #
I
Thermal circuit signal: the signal is low when THRMTRIP # model, the heat from the processor circuit model, ICH9 immediately into S5 state. ICH9 will not be allowed from the processor to stop waiting for the signal to return it into the S5 state.
SLP_S3 #
O
S3 Sleep Control signal: SLP_S3 # is the power level control.
When entering S3 (suspend to RAM), S4 (suspend to disk), S5 (soft off) state when this signal to switch off all non-critical system power.
SLP_S4 #
O
S4 Sleep control signal: SLP_S4 # i is the power level control signal when entering S4 (suspend to disk), S5 (soft off) state when this signal to switch off all non-critical system power.
Note: The Pin Pin ICH9 previously used to control the DRAM power circulation.
Note: in a system of support for Intel's AMT, this signal is used to control the DRAM power,
comment: In the M1 state (when the host is in S3, S4, S5 status and operational subsystems running) This signal is forced high with SLP_M # to DIMM provide sufficient power for the operational subsystem.
SLP_S5 #
O
S5 Sleep Control signal: SLP_S5 # is a power level control signal when the system into the S5 (soft off) state SLP_S5 # used to shut down all non-critical power systems.
SLP_M #
O
Operational sleep control signal: Intel AMT for power level control subsystem. If there is no operational engine firmware, SLP_M # sync with SLP_S3 #.
S4_STATE # / GPIO26
O
S4 state pointer signal: when the machine is in S4 or S5 state, the signal is active low. When the machine is operable in the S3 state, together with the engine forced SLP_S4 # SLP_S4 # is high, this signal can be used for other devices to understand the current state of the machine
Southbridge portion of the signal power management so much, perhaps in the translation and understanding there are still some problems, please contact me to discuss, we progress together.
We may encounter in the maintenance of the CPU is not the clock, replace the clock chip, crystal, etc., or no repair, how to do mile? ? ? You tested Southbridge STP_CPU # signal?
STP_PCI # / GPIO15 (only for desktop computers)
O
Close the PCI clock signal: When STP_PCI # signal is low, the external clock pulse generator will turn off PCI clock signal. It was formerly used in notebook computers up to support PCI CLKRUN # protocol.
In Sx (S0, S1, S3, S4, S5) state, when the system opens the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller selects the main clock the frequency.
The signal on the desktop platform GPIO signals can be converted into, then it does not support Intel AMT or ASF.
STP_CPU # / GPIO25 (only for desktop computers)
O
Block the CPU clock signal: This signal is valid when the command is an external clock generator off the CPU clock, on a laptop computer used to support the C3 state. In Sx (S0, S1, S3, S4, S5) state, when the system opens the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller selects the main clock the frequency.
The signal on the desktop platform GPIO signals can be converted into, then it does not support Intel AMT or ASF.
BATLOW # (only for notebook) / TP0 (only for desktop computers)
I
Battery low signal: This input signal from the laptop battery pack, when the battery is sufficient to maintain the system sends a signal. The signal is active it will prevent the system from S3, S4, S5 wake up can also cause a SMI # signal active.
DPRSLPVR (only for laptops) / GPIO16
O
Deeper sleep - regulator signal: This signal is used in the C4 state, the VRM voltage drops lower. When this signal is high, the regulator output voltage is less deep sleep. The signal is low (default is low), the normal voltage regulator output. (Regulator means VRM)
DPRSTP # (only for notebook) / TP1 (only for desktop computers)
O
Depth of the stop signal: This signal is DPRSLPVR a copy, active low.
Type
Description
PWRBTN #
I
Power Button:. The power button will cause SMI # or SCI to indicate a system sleep state. If the system is asleep, then this signal will trigger a wake event. If PWRBTN # have effect when the room more than 4s, regardless of the system in the S0, S1, S3, S4 state, then will the unconditional transition to S5 state. This signal has an internal pull-up resistor and the input features of a 16ms debounce design.
RI #
I
Sound alert: This signal is a signal input from the Modem. It allows a wake-up event, when a power failure protection
SYS_RESET #
I
System Reset: This signal after the anti-rebound force an internal reset. If the SMBus is idle, South Bridge will be immediately reset, the other, forcing a reset in the system before, SYS_RESET # will wait for 25ms ± 2ms until the SMBus Free
RSMRST #
I
Restore normal reset signal:
This signal is used to reset the logic of power is restored, all the power of this signal is valid for at least 10ms will work, when the lift is valid, the signal is pending bus a sign of stability
LAN_RST #
I
LAN Reset:
When this signal is valid when the internal controller to reset the LAN, the LAN's ccLAN3_3 and VccLAN1_05 and VccCL3_3 normal state of the signal power to be effective. When the release is valid, the signal is a sign of a stable LAN Bus Notes: 1 lift effective in RSMRST # before LAN_RST # must be valid.
(2) effective after the PWROK, LAN_RST # must be valid.
3 in VccLAN3_3 and VccLAN1_05 and VccCL3_3 power under normal conditions are to be effective LAN_RST # 1ms.
4 Integrated LAN without LAN_RST # if it can be connected to Vss.
WAKE #
I
PCI Express * Wake Event: Sideband wake signal on the PCI Express slot and issue a wake-up request signal components
MCH_SYNC #
I
Northbridge sync signal: This input signal is phase with PWROK internally, and the signal is connected to the Northbridge ICH_SYNC # output.
SUS_STAT # / LPC PD #
O
Suspend state signal: This signal indicates that the system is about to enter an effective low-power state. It monitors these devices and the memory from the normal mode to enter the suspend mode, it can be used to isolate the output of other peripheral devices and turn them off, the signal in LPC I / F on the call LPCPD # to achieve.
SUSCLK
O
Hang the clock signal: This clock is RTC chip clock generator generates the clock through the other to the output.
VRMPWRGD
I
CPU Power Good Signal: This signal is directly connected to the CPU power management chip, the signal is normal that VRM is stable. The input signal is the phase of the internal PWROK.
This signal is normal at the time suspended
CK_PWRGD
O
Clock pulse generator power normal signal: When the main power efficient clock generator when the signal to go, when SLP_S3 # and VRMPWRGD two signals are high when the signal is active high
PMSYNC # (only for notebook) / GPIO0
O
Sync signal power management: When the signal is active, C5 or C6 in the exit when the signal from the North Bridge to CPUSLP # This pin is invalid.
This signal can also be used for GPIO.
CLKRUN # (only for notebook) / GPIO32 (only for desktop computers)
I / O
PCI clock run signal: This signal is used to support the PCI
CLKRUN agreement. When connected to external devices need to apply preventive restarting the clock or clock stopped
PLTRST #
O
Total reset signal: PLTRST # is Intel ® ICH9 always reset the entire platform (such as: I / O, BIOS chip, card, Northbridge, etc.). During power and when S / W reset control signal through the register (I / O registers CF9h) initiates a hard reset sequence ICH9 determine PLTRST # state. High in PWROK and VRMPWRGD ICH9 driver PLTRST # after at least 1 ms is invalid. When initialized by reset control register (I / O registers CF9h) when the ICH9 driver PLTRST # is valid for at least 1 millisecond.
Note: Only VccSus3_3 normal PLTRST # This signal is applied.
THRM #
I
Thermal alarm signal: activation THRM # signal to low external hardware to generate an SMI # or SCI signal
THRMTRIP #
I
Thermal circuit signal: the signal is low when THRMTRIP # model, the heat from the processor circuit model, ICH9 immediately into S5 state. ICH9 will not be allowed from the processor to stop waiting for the signal to return it into the S5 state.
SLP_S3 #
O
S3 Sleep Control signal: SLP_S3 # is the power level control.
When entering S3 (suspend to RAM), S4 (suspend to disk), S5 (soft off) state when this signal to switch off all non-critical system power.
SLP_S4 #
O
S4 Sleep control signal: SLP_S4 # i is the power level control signal when entering S4 (suspend to disk), S5 (soft off) state when this signal to switch off all non-critical system power.
Note: The Pin Pin ICH9 previously used to control the DRAM power circulation.
Note: in a system of support for Intel's AMT, this signal is used to control the DRAM power,
comment: In the M1 state (when the host is in S3, S4, S5 status and operational subsystems running) This signal is forced high with SLP_M # to DIMM provide sufficient power for the operational subsystem.
SLP_S5 #
O
S5 Sleep Control signal: SLP_S5 # is a power level control signal when the system into the S5 (soft off) state SLP_S5 # used to shut down all non-critical power systems.
SLP_M #
O
Operational sleep control signal: Intel AMT for power level control subsystem. If there is no operational engine firmware, SLP_M # sync with SLP_S3 #.
S4_STATE # / GPIO26
O
S4 state pointer signal: when the machine is in S4 or S5 state, the signal is active low. When the machine is operable in the S3 state, together with the engine forced SLP_S4 # SLP_S4 # is high, this signal can be used for other devices to understand the current state of the machine
Southbridge portion of the signal power management so much, perhaps in the translation and understanding there are still some problems, please contact me to discuss, we progress together.
We may encounter in the maintenance of the CPU is not the clock, replace the clock chip, crystal, etc., or no repair, how to do mile? ? ? You tested Southbridge STP_CPU # signal?
STP_PCI # / GPIO15 (only for desktop computers)
O
Close the PCI clock signal: When STP_PCI # signal is low, the external clock pulse generator will turn off PCI clock signal. It was formerly used in notebook computers up to support PCI CLKRUN # protocol.
In Sx (S0, S1, S3, S4, S5) state, when the system opens the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller selects the main clock the frequency.
The signal on the desktop platform GPIO signals can be converted into, then it does not support Intel AMT or ASF.
STP_CPU # / GPIO25 (only for desktop computers)
O
Block the CPU clock signal: This signal is valid when the command is an external clock generator off the CPU clock, on a laptop computer used to support the C3 state. In Sx (S0, S1, S3, S4, S5) state, when the system opens the Intel AMT or ASF, in order to support the Moff / Sx to M1/Sx conversion, this pin is used to inform the clock controller selects the main clock the frequency.
The signal on the desktop platform GPIO signals can be converted into, then it does not support Intel AMT or ASF.
BATLOW # (only for notebook) / TP0 (only for desktop computers)
I
Battery low signal: This input signal from the laptop battery pack, when the battery is sufficient to maintain the system sends a signal. The signal is active it will prevent the system from S3, S4, S5 wake up can also cause a SMI # signal active.
DPRSLPVR (only for laptops) / GPIO16
O
Deeper sleep - regulator signal: This signal is used in the C4 state, the VRM voltage drops lower. When this signal is high, the regulator output voltage is less deep sleep. The signal is low (default is low), the normal voltage regulator output. (Regulator means VRM)
DPRSTP # (only for notebook) / TP1 (only for desktop computers)
O
Depth of the stop signal: This signal is DPRSLPVR a copy, active low.